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D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS[64/72]D16000GU-[7/8]-A HYS[64/72]D32020GU-[7/8]-A
Unbuff ered DDR SDRAM- Modul es DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2004-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS[64/72]D16000GU-[7/8]-A HYS[64/72]D32020GU-[7/8]-A
Unbuff ered DDR SDRAM- Modul es DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS[64/72]D16000GU-[7/8]-A, HYS[64/72]D32020GU-[7/8]-A Revision History: Previous Version: Page all Rev. 1.03 Rev. 1.02 2004-01 2003-11
Subjects (major changes since last revision) Editorial changes
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 18 20
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
5
Rev. 1.03, 2004-01
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Overview
1
1.1
* * * * * * * * * * *
Overview
Features
184-pin Unbuffered 8-Byte Dual-In-Line DDR SDRAM non-parity and ECC-Modules for PC and Server main memory applications One rank 16M x 64, 16M x 72 and two rank 32M x 64, 32M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single + 2.5 V ( 0.2 V) power supply Built with 128 Mb DDR SDRAMs organised as 16Mb x 8 in 66-Lead TSOPII package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. JEDEC standard reference layout Gold plated contacts Performance -8/-7 -7 Component Module @CL2.5 @CL2 DDR266A PC2100-2033 -8 DDR200 PC1600-2022 125 100 Unit -- -- MHz MHz
Table 1
Part Number Speed Code Speed Grade max. Clock Frequency
fCK2.5 fCK2
143 133
1.2
Description
The HYS64/72D16000GU and HYS64/72D32020GU are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 16M x 64 and 32M x 64 for non-parity and 16M x 72 and 32M x 72 for ECC main memory applications. The memory array is designed with 128Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Overview Table 2 Type PC2100 (CL=2): HYS64D16000GU-7-A HYS72D16000GU-7-A HYS64D32020GU-7-A HYS72D32020GU-7-A PC1600 (CL=2): HYS64D16000GU-8-A HYS72D16000GU-8-A HYS64D32020GU-8-A HYS72D32020GU-8-A PC1600-20220-A1 PC1600-20220-A1 PC1600-20220-B1 PC1600-20220-B1 one rank 128 MB DIMM two ranks 256 MB DIMM 128 MBit (x8) 128 MBit (x8) PC2100-20330-A1 PC2100-20330-A1 PC2100-20330-B1 PC2100-20330-B1 one rank 128 MB DIMM two ranks 256 MB DIMM 128 MBit (x8) 128 MBit (x8) Ordering Information Compliance Code Description SDRAM Technology
one rank 128 MB ECC-DIMM 128 MBit (x8) two ranks 256 MB ECC-DIMM 128 MBit (x8)
one rank 128 MB ECC-DIMM 128 MBit (x8) two ranks 256 MB ECC-DIMM 128 MBit (x8)
Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 72D32020GU-8-A, indicating Rev.A dies are used for the SDRAM components. The Compliance Code is printed on the module labels and describes the speed sort fe. "PC2100", the latencies (f.e. "20330" means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module.
Data Sheet
7
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
2
Table 3 Symbol A0 - A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7
Pin Configuration
Pin Definitions and Functions Type1) I I I/O I/O I I I/O I I I I/O I PWR GND PWR PWR AI PWR I I/O I NC Function Address Inputs Bank Selects Data Input/Output Check Bits (x72 organization only) Command Inputs Clock Enable SDRAM low data strobes SDRAM clock (positive lines) SDRAM clock (negative lines) SDRAM low data mask/ high data strobes Chip Selects for Rank0 and Rank1 Power (+2.5 V) Ground I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select Not Connected
RAS, CAS, WE CKE0 - CKE1 DQS0 - DQS8 CK0 - CK2, CK0 - CK2 DM0 - DM8 DQS9 - DQS17 S0, S1 VDD VSS VDDQ VDDID VREF VDDSPD SCL SDA SA0 - SA2 NC
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration Table 4 Frontside PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol PIN# 48 49 50 51 52 Symbol A0 NC / CB2 Pin Configuration Backside PIN# 93 94 95 96 97 98 99 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ32 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 Symbol PIN# 140 141 142 143 144 Symbol NC / DM8/DQS17 A10 NC / CB6
VREF
DQ0
VSS
DQ4 DQ5
VSS
DQ1 DQS0 DQ2
VSS
NC / CB3 BA1 Key
VDDQD
DM0/DQS9 DQ6 DQ7
VDDQD
NC / CB7 Key
VDD
DQ3 NC NC
VSS
NC NC NC
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
VSS
DQ36 DQ37
VDDQ
DQ33 DQS4 DQ34
VSS
DQ8 DQ9 DQS1
VDD
DM4/DQS13 DQ38 DQ39
VDDQ
DQ12 DQ13 DM1/DQS10
VSS
BA0 DQ35 DQ40
VDDQ
CK1 CK1
VSS
DQ44 RAS DQ45
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VSS
DQ10 DQ11 CKE0
VDDQ
S0 S1 DM5/DQS14
VDDQ
NC (BA2) DQ20 NC / A12
VSS
DQS5 DQ42 DQ43
VDDQ
DQ16 DQ17 DQS2
VSS
DQ46 DQ47 NC
VSS
DQ21 A11 DM2/DQS11
VDD
NC DQ48 DQ49
VSS
A9 DQ18 A7
VDDQ
DQ52 DQ53 NC (A13)
VDD
DQ22 A8 DQ23
VSS
CK2 CK2
VDDQ
DQ19 A5 DQ24
VDD
DM6/DQS15 DQ54 DQ55
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VSS
DQ25 DQS3 A4
VDDQ
NC DQ60 DQ61
VSS VDDID
DQ56 DQ57
VDDQ
DM3/DQS12 A3 DQ30
VDD
DQ26
VSS
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
Data Sheet
9
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration Table 4 Frontside PIN# 40 41 42 43 44 45 46 47 Symbol DQ27 A2 PIN# 85 86 87 88 89 90 91 92 Symbol Pin Configuration (cont'd) Backside PIN# 132 133 134 135 136 137 138 139 Symbol PIN# 177 178 179 180 181 182 183 184 Symbol DM7/DQS16 DQ62 DQ63
VDD
DQS7 DQ58 DQ59
VSS
DQ31 NC / CB4 NC / CB5
VSS
A1 NC / CB0 NC / CB1
VDDQ
SA0 SA1 SA2
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDD
NC / DQS8
VSS
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("not connected") on x64 organised non-ECC modules.
Table 5 Density
Address Format Organization Memory Banks SDRAMs # of SDRAMs # of row/bank/ columns bits 12/2/10 12/2/10 12/2/10 12/2/10 Refresh Period Interval
128 MB 128 MB 256 MB 256 MB
16M x 64 16M x 72 32M x 64 32M x 72
1 1 2 2
16M x 8 16M x 8 16M x 8 16M x 8
8 9 16 18
4K 4K 4K 4K
64 ms 64 ms 64 ms 64 ms
15.6 s 15.6 s 15.6 s 15.6 s
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("no-connects") on x64 organised non-ECC modules. A12 is used for 256 Mbit based modules only.
Data Sheet
10
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4/DQS13
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams BA0 - BA1 A0 - A13 RAS CAS CKE0 WE BA0-BA1: SDRAMs D0 - D7 A0-A13: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 VDD SPD VDD/VDDQ VREF VSS VDDID SPD D0 - D7 D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5% 4. VDDID strap connections (for memory device VDD , V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ . 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms +5%
Figure 1
Block Diagram: One Rank 16M x 64 DDR SDRAM DIMM Module HYS64D16000GU using x8 organized SDRAMs
Data Sheet
11
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D8
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D12
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D9
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D10
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D11
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
VDD SPD VDD/VDDQ VREF VSS VDDID
SPD D0 - D15 D0 - D15 D0 - D15 Strap: see Note 4 SCL WP A0 SA0 SDA A1 SA1 A2 SA2 Serial PD
BA0 - BA1 A0 - An CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D15 A0-An: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D15
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 2
Block Diagram: Two Rank 32M x 64 DDR SDRAM DIMM Modules HYS64D32020GU using x8 Organized SDRAMs
Data Sheet
12
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
DQS8 DM8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
Serial PD SCL WP A0 SA0 SDA A1 SA1 A2 SA2
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 3 SDRAMs 3 SDRAMs 3 SDRAMs
D8
* Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D8 A0-A13: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 VDDSPD VDD/VDDQ VREF VSS VDDID
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be SPD maintained as shown. D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections D0 - D8 (for memory device VDD, V DDQ ): D0 - D8 STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ. Strap: see Note 4 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm +5%
Figure 3
Block Diagram: One Rank 16M x 72 DDR SDRAM DIMM Module HYS72D16000GU using x8 organized SDRAMs
Data Sheet
13
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D9
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D10
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D11
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D12
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
VDD SPD VDD/VDDQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
SPD D0 - D17 D0 - D17 D0 - D17
VREF VSS VDDID Strap: see Note 4
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 6 SDRAMs 6 SDRAMs 6 SDRAMs
D8
D17
BA0 - BA1 A0 - A13 CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D17 A0-A13: SDRAMs D0 - D17 CKE: SDRAMs D9 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D17 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections SDA (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 4
Block Diagram: Two Rank 32M x 72 DDR SDRAM DIMM Modules HYS72D32020GU using x8 Organized SDRAMs 14 Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
Data Sheet
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Pin Configuration
6 DRAM Loads
DR AM 1
4 DRAM Loads DR AM 1
DRAM2 CK DIMM Connector CK R = 120 DRAM3 DIMM Connector DR AM4 DR AM5 R =120
DRAM2 Cap.
Cap. DR AM5
DR AM6
DRAM6 DR AM 1
3 DRAM Loads
DR AM 1
2 DRAM Loads Cap.
Cap. R =120 DIMM Connector DR AM3 DIMM Connector
R =120
Cap.
Cap. Cap. DR AM5 Cap. Cap. DR AM5
Figure 5
Clock Net Wiring
Data Sheet
15
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
Data Sheet
16
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 7 Parameter
Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.3 2.3 0 Values Typ. 2.5 2.5 2.5 Max. 2.7 2.7 3.6 0 V V V V
2)
Unit Note/Test Condition 1)
VDD Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF I/O Termination Voltage VTT
Device Supply Voltage (System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current
-- --
3) 4)
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
1.4 V --
7) 7) 7)
VIN(DC) VID(DC)
VIRatio
7)5)
6)
II
-2
2
A
Any input 0 V VIN VDD; All other pins not under test = 0 V 7)8) DQs are disabled; 0 V VOUT VDDQ 7)
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 7) VOUT = 0.35 V 7)
2) Under all conditions, VDDQ must be less than or equal to VDD. 3) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5) VID is the magnitude of the difference between the input level on CK and the input level on CK. 6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 7) Inputs are not recognized as valid until VREF stabilizes. 8) Values are shown per component
Data Sheet
17
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3.2
Table 8 Parameter
Current Specification and Conditions
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
18
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 9
IDD Specification and Conditions -8/-7
HYS64D16000GU-8-A HYS64D16000GU-7-A HYS72D16000GU-8-A HYS72D16000GU-8-A HYS64D32020GU-8-A HYS64D32020GU-7-A HYS72D32020GU-8-A HYS72D32020GU-7-A Unit Note 1)2)
Part Number & Organization
128MB x64 1 Rank -8 680 800 36 280 280 120 280 720 760 1440 20 2160 -7 max 720 880 40 360 360 120 360 880 880 1520 20 2240
128MB x72 1 Rank -8 765 900 40.5 315 315 135 315 810 855 1620 22.5 2430 -7 max 810 990 45 405 405 135 405 990 990 1710 22.5 2520
256MB x64 2 Ranks -8 960 1080 72 560 560 240 560 1000 1040 1720 40 2440 -7 max 1080 1240 80 720 720 240 720 1240 1240 1880 40 2600
256MB x72 2 Ranks -8 1080 1215 81 630 630 270 630 1125 1170 1935 45 2745 -7 max 1215 1395 90 810 810 270 810 1395 1395 2115 45 2925 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
19
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
3.3
Table 10 Parameter
AC Characteristics
AC Timing - Absolute Specifications -8/-7 Symbol Min. -8 DDR200 Max. +0.8 +0.8 0.55 0.55 12 12 12 -- -- -- -- +0.8 +0.8 1.25 +0.6 1.0 Min. -0.75 -0.75 0.45 0.45 7 7.5 -- 0.5 0.5 2.2 1.75 -0.75 -0.75 0.75 -- -- -7 DDR266A Max. +0.75 +0.75 0.55 0.55 12 12 -- -- -- -- -- +0.75 +0.75 1.25 +0.5 0.75 -- -- -- -- -- -- 0.60 -- -- -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle)
tAC tDQSCK tCH tCL tHP tCK2.5 tCK2 tCK1.5 tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ tQHS tQH tDQSL,H
-0.8 -0.8 0.45 0.45 8 10 10 0.6 0.6 2.5 2.0 -0.8 -0.8 0.75 -- --
tCK tCK
ns ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
tCK
ns ns ns
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)
tHP - -- tQHS
0.35 0.2 0.2 2 0 0.40 0.25 1.1 1.1 -- -- -- -- -- 0.60 -- -- --
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.9 1.0
tCK tCK tCK tCK
ns
2)3)4)5)
DQS falling edge to CK setup time (write tDSS cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time
2)3)4)5)
tDSH tMRD tWPRES tWPST tWPRE tIS
2)3)4)5)
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Data Sheet
20
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 10 Parameter AC Timing - Absolute Specifications -8/-7 Symbol Min. Address and control input hold time -8 DDR200 Max. -- -- 1.1 1.1 -- 0.60 120E+3 -- -- -- -- -- -- -- Min. 0.9 1.0 0.9 NA NA 0.40 45 65 75 20 20 20 15 15 0.60 -- -- -- -- -- -- -- -7 DDR266A Max. -- -- 1.1 ns ns fast slew rate
3)4)5)6)10)
Unit Note/ Test Condition 1)
tIH
1.1 1.1
slow slew rate
3)4)5)6)10)
tRPRE tRPRE1.5 Read preamble setup time tRPRES Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC
Read preamble period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
0.9 0.9 1.5 0.40 50 70 80 20 20 20 15 15
tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)11)
2)3)4)5)12) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK
ns ns ns ns ns ns ns
120E+3 ns
tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR tWTR1.5 tXSNR tXSRD tREFI
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)13)
(twr/tCK) + (trp/tCK) 1 2 80 200 -- -- -- -- -- 7.8 1 -- 75 200 -- -- -- -- -- 7.8
tCK tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)14)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR266, and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
Data Sheet
21
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Electrical Characteristics
10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) CAS Latency 1.5 operation is supported on DDR200 devices only 12) tRPRES is defined for CL = 1.5 operation only 13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
22
Rev. 1.02, 2003-11
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
SPD Contents
4
Table 11 Byte#
SPD Contents
SPD Codes for PC1600 Modules -8 Description 128MB x64 1rank -8 hex. 128 256 DDR-SDRAM 12 10 1/2 x64/x72 0 SSTL_2.5 8 ns 0.8 ns non-ECC/ECC Self-Refresh 15.6 ms x8 80 08 07 0C 0A 01 40 00 04 80 80 00 80 08 00 01 128MB x72 1rank -8 hex. 80 08 07 0C 0A 01 48 00 04 80 80 02 80 08 08 01 128MB x64 2ranks -8 hex. 80 08 07 0C 0A 02 40 00 04 80 80 00 80 08 00 01 128MB x64 2ranks -8 hex. 80 08 07 0C 0A 02 48 00 04 80 80 02 80 08 08 01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary
Error Checking SDRAM Data na/x8 Witdh Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time for CL = 1.5
tCCD = 1 CLK
16 17 18 19 20 21 22 23 24 25
2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered - 10 ns 0.8 ns not supported
0E 04 0C 01 02 20 C0 A0 80 00
0E 04 0C 01 02 20 C0 A0 80 00
0E 04 0C 01 02 20 C0 A0 80 00
0E 04 0C 01 02 20 C0 A0 80 00
Data Sheet
23
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
SPD Contents Table 11 Byte# SPD Codes for PC1600 Modules -8 (cont'd) Description 128MB x64 1rank -8 hex. 26 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD not supported 20 ns 15 ns 00 50 3C 50 32 20 B0 B0 60 60 46 50 30 3C A0 00 00 84 128MB x72 1rank -8 hex. 00 50 3C 50 32 20 B0 B0 60 60 46 50 30 3C A0 00 00 96 128MB x64 2ranks -8 hex. 00 50 3C 50 32 20 B0 B0 60 60 46 50 30 3C A0 00 00 85 128MB x64 2ranks -8 hex. 00 50 3C 50 32 20 B0 B0 60 60 46 50 30 3C A0 00 00 97
Minimum RAS to CAS Delay 20 ns
tRCD
Minimum RAS Pulse Width 50 ns 128 MByte 1.1 ns
tRAS
Module Bank Density (per Bank) Addr. and Command Setup Time
Addr. and Command Hold 1.1 ns Time Data Input Setup Time Data Input Hold Time Superset Information 0.6 ns 0.6 ns -
Minimum Core Cycle Time 70 ns
tRC
Min. Auto Refresh Cycle Time tFRC Cmd 80 ns
Maximum Clock Cycle Time 12 ns
tCK
Max. DQS-DQ Skew tDQSQ 0.6 ns X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures Codes Manufactures Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - JEDEC 1.0 ns - Revision 0.0 - ID - - - - - - - - - Infineon - - - - - - - Infineon - - - - - - - Infineon - - - - - - - Infineon - - - - - - -
128 to 255 open for Customer use
Data Sheet
24
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
SPD Contents
Table 12 Byte#
SPD Codes for PC2100 Modules -7 Description 128MB x64 1rank -7 hex. 128 256 DDR-SDRAM 12 10 1/2 x64/x72 0 SSTL_2.5 7 ns 0.75 ns non-ECC/ECC Self-Refresh 15.6 ms x8 80 08 07 0C 0A 01 40 00 04 70 75 00 80 08 00 01 128MB x72 1rank -7 hex. 80 08 07 0C 0A 01 48 00 04 70 75 02 80 08 08 01 128MB x64 2ranks -7 hex. 80 08 07 0C 0A 02 40 00 04 70 75 00 80 08 00 01 128MB x64 2ranks -7 hex. 80 08 07 0C 0A 02 48 00 04 70 75 02 80 08 08 01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary
Error Checking SDRAM Data na/x8 Witdh Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time for CL = 1.5 Access Time from Clock at CL = 1.5
tCCD = 1 CLK
16 17 18 19 20 21 22 23 24 25 26
2, 4 & 8 4 CS latency = 0 Write latency = 1 unbuffered - 7.5 ns 0.75 ns not supported not supported
0E 04 01 02 20 C0 75 75 00 00
0E 04 0C 01 02 20 C0 75 75 00 00
0E 04 0C 01 02 20 C0 75 75 00 00
0E 04 0C 01 02 20 C0 75 75 00 00
CAS latency = 2 & 2.5 0C
Data Sheet
25
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
SPD Contents Table 12 Byte# SPD Codes for PC2100 Modules -7 (cont'd) Description 128MB x64 1rank -7 hex. 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD 20 ns 15 ns 50 3C 50 2D 20 90 90 50 50 41 4B 30 32 75 00 00 8F C1 Infineon - - - - - - - 128MB x72 1rank -7 hex. 50 3C 50 2D 20 90 90 50 50 41 4B 30 32 75 00 00 8F C1 Infineon - - - - - - - 128MB x64 2ranks -7 hex. 50 3C 50 2D 20 90 90 50 50 41 4B 30 32 75 00 00 8F C1 Infineon - - - - - - - 128MB x64 2ranks -7 hex. 50 3C 50 2D 20 90 90 50 50 41 4B 30 32 75 00 00 8F C1 Infineon - - - - - - -
Minimum RAS to CAS Delay 20 ns
tRCD
Minimum RAS Pulse Width 45 ns 128 MByte 0.9 ns
tRAS
Module Bank Density (per Bank) Addr. and Command Setup Time
Addr. and Command Hold 0.9 ns Time Data Input Setup Time Data Input Hold Time Superset Information 0.5 ns 0.5 ns -
Minimum Core Cycle Time 65 ns
tRC
Min. Auto Refresh Cycle Time tFRC Cmd 75 ns
Maximum Clock Cycle Time 12 ns
tCK
Max. DQS-DQ Skew tDQSQ 0.5 ns X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures Codes Manufactures Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - JEDEC 0.75 ns - Revision 0.0 - ID - - - - - - - - -
128 to 255 open for Customer use
Data Sheet
26
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 4 MAX.
1)
0.15 A B C
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 6 DDR-SDRAM DIMM Module Package
Data Sheet
27
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 7 Package Outlines -Raw Card A1 (One Rank Modules)
Data Sheet
28
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
HYS[64/72]D[16000/32020]GU-[7/8]-A Unbuffered DDR SDRAM-Modules
Package Outlines
DDR-SDRAM DIMM Module Package two banks modules
133.35 + 0.15
4.0 max.
Front View
+ 0.13 -
4.0
*) 2.3 typ.
31.75
pin 1 64.77
2.3 typ.
52
53 49.53
92
1.27 + 0.1
6.62
Backside View
pin 93 17.80 10.0 144 145 184
2.5D
*)
3 *) on ECC modules only
3
Detail of Contacts A 0.20 + 0.15 2.5 + 0.20 -
Detail of Contacts B 6.35 0.9R 3.8 typ. 1.8 2.175
L-DIM-1849d
1 + 0.05
1.27
Figure 8
Package Outlines - Raw Card B1 (Two Rank Modules)
Data Sheet
29
Rev. 1.03, 2004-01 10292003-WLD7-IJ5Z
http://www.infineon.com
Published by Infineon Technologies AG

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